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Synopsys, Inc. announced a state-of-the-art artificial intelligence (AI) enabled formal verification app, Regression Mode Accelerator, as part of the Synopsys VC Formal^® solution. This VC Formal app leverages state-of-the-art machine learning algorithms to deliver 10X speed-up in formal property verification during the design and verification cycle. Along with significant performance speed-up, use of this app accelerates formal property verification to achieve better convergence of formal proofs for subsequent runs. The Regression Mode Accelerator app also allows for significant saving of compute resources in nightly regressions for the verification of complex system-on-chip (SoC) designs to enable running formal verification in situations previously deemed impractical.

“As a leading integrated device manufacturer delivering solutions that are key to innovation and advancing the state-of-the-art in Smart Driving and the Internet of Things, including Smart Industry, ST’s designers need a formal verification solution that provides best-in-class performance, ease-of-use, and quality of results,” said David Vincenzoni, R&D Design Manager at STMicroelectronics. “The newly introduced VC Formal Regression Mode Accelerator app consistently delivered an order-of-magnitude performance improvement along with improved convergence of additional inconclusive properties for the most complex SystemVerilog Assertions on our design blocks.”

Increasing SoC complexity combined with rising time-to-market pressures are driving a continuous need for innovation in formal property verification performance and throughput. Synopsys VC Formal, with its comprehensive set of formal apps, including Property Verification (FPV), Sequential Equivalence Checks (SEQ), Register Verification (FRV), Formal Coverage Analyzer (FCA), Connectivity Checking (CC) and Automatic Extraction of Properties (AEP), has delivered faster property convergence for many different use cases at ST. The native integration of VC Formal with Synopsys’ VCS^®functional verification solution and Verdi^® automated debug system enables design and verification teams to easily leverage formal technologies and automate root-cause analysis of formal results. Additionally, the native integration of VCS’ robust coverage engines in VC Formal facilitates easy insertion of formal analysis into the existing verification environment.

“Machine-learning has emerged as a powerful technology for addressing the verification of highly-complex and leading-edge designs,” said Manish Pandey, Synopsys Fellow in the Verification Group. “We have long collaborated with industry leaders like ST on the delivery of comprehensive verification solutions for advanced SoCs. Throughout these collaborations, we are broadening our investment in AI-enabled technologies into verification flows and methodologies, enabling faster time-to-market.”

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