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An interview with Simon Rance, Director of Product Management and Strategic Marketing at Keysight Technologies

Simon Rance, Director of Product Management and Strategic Marketing at Keysight Technologies

Chiplets are making big waves in the semiconductor industry, with global market size expected to grow 71.3% from 2023 to 2031. With integration of multiple technologies, semiconductor design teams are reinvigorating Moore’s Law, by paving the way for designs featuring multi-billion transistors and hundreds of semiconductor intellectual properties (IPs).

However, powerful chiplet-based architectures have also introduced a new level of complexity in managing intellectual properties (IPs), from stringent export controls to compliances and IP security risks.

To navigate these complexities, companies need to adopt a comprehensive approach to IP lifecycle management, one that encompasses more than just the IP itself and considers a holistic perspective of its lifecycle. Keysight Director of Product Management, Simon Rance, talks about the challenges associated with IP management for chiplets and how design teams can improve IP security and compliance.

Question 1: What are the key challenges associated with IP management for chiplet projects?

There is much more IP reuse due to the complexity and shorter timeframes for new designs. Most design teams deal with in-house IPs – often considered a company’s “secret sauce”—and IPs licenced from third-party vendors. Such a mix underscores the necessity for a unified platform capable of distinguishing between internal and third-party IPs while providing visibility to various attributes of each IP.

A chiplet-based design can feature diverse IPs across different process nodes. As the design engineers must select the right IP based on process technologies, origins, and licensing details, the traditional practice of tracking IPs through spreadsheets has become obsolete. Questions such as whether the existing license permits using the IP in a chiplet-based design, are important.

Moreover, implementing a stringent verification process is imperative to guarantee that the integrated IP blocks function cohesively and comply with all design standards and requirements. Given these chiplets are expected to remain operational for over 10 or 20 years, they present unique challenges in verifying and maintaining these IPs throughout their lifecycle, especially as personnel changes occur over time.

Question 2:  How do design teams improve IP security and ensure compliance in a multi-vendor chiplet design environment?

The wider adoption of chiplet technology has significantly raised the stakes for IP security and compliance. Here are my three recommendations.

First, rigorous access controls play a pivotal role in securing semiconductor IPs. The IP management systems should limit access based on defined criteria. This can include job functions, geographic locations, and security levels. Given increasingly strict export controls, design companies must incorporate geofencing capabilities that restrict access to certain IPs based on the physical location of an individual, whether they are contractors, designers, or architects. For large-scale, multi-vendor chiplet projects, companies should also consider adding custom checkpoints, such as limiting a specific IP to a single design, thereby preventing unauthorised reuse in subsequent projects.

Second, an integral component of managing IP lifecycles is the capability to verify the licencing status of IPs, ensuring that design teams have permission to use them. For chiplet-based designs, this verification process requires visibility on whether an IP has already been used in another project within the company and whether it is available for use in new designs. Such measures are essential for preventing licensing violations and the potential legal and financial repercussions.

Third, precise tracing of IP usage is critical for maintaining security and compliance. This helps streamline engineering change orders (ECOs) and ensure adherence to industry standards like functional safety (such as ISO 26262 for automotive). An effective IP management approach should be capable of providing detailed reports on the exact usage of an IP, its dependencies, and the hierarchy within its designs. This enables IP managers to accurately trace critical information throughout the IP lifecycle, enhancing design traceability with one single source of truth.

Question 3: Can you share some best practices for facilitating collaboration between design teams, especially when they’re working on chiplets?

The shift towards chiplet-based designs has underscored the need for a centralised IP management strategy for robust collaboration. This ensures that every team member works from the latest libraries and traceable lineage for each piece of IP. In a multi-vendor environment, the security of sensitive IP becomes paramount. For instance, when it comes to testing die-to-die interconnects, all team members should gain a clear view of which data can be shared with other vendors and which cannot.

Securing data during handoffs, whether through workflow tools or between teams, is also a critical concern. At Keysight, we’ve implemented encrypted data transfers and secure file-sharing protocols to safeguard IP information. For companies in the aerospace and defense industries, the need for secure workflows pushes demand for integrating blockchain technology into IP management.

Question 4: How do you integrate workflows for chiplet designs with various EDA tools?

Integrating workflows for chiplet designs with various Electronic Design Automation (EDA) tools is a complex process.

Traditional, home-grown solutions for data import/export become more cumbersome and error-prone. For instance, when integrating different chiplets, how are we verifying the interconnect between chiplet one and chiplet two across the enterprise? How can we track the history of an IP to see if it has been successfully used in any previous system-on-chip (SoC) projects?

All of these types of data exchange and communication should happen within one platform so that everybody knows where to find the data, trace the IP usage and project notes, and do an audit report of the IP.

With this in mind, companies need a unified environment that integrates with all EDA tools. This way, teams can gain a a comprehensive view of all design data and IPs at the enterprise level. By keeping all data and IPs within a unified platform, businesses can also mitigate the risk of siloed information and ensure that all team members can access the latest, accurate versions.

At Keysight, we empower our customers with a unified environment integrated with all EDA tools from Synopsys, Cadence, Siemens EDA, and our own Advanced Design System (ADS) platform. Keysight IP Management (HUB) provides a comprehensive view of all design data and IPs at the enterprise level. By keeping all data and IPs within a unified platform, we mitigate the risk of siloed information and ensure that all team members can access the latest, accurate versions. To further empower design teams to accelerate time-to-market for their chiplet-based designs, we’ve introduced four features within HUB:

• Easy Access to Commands. We’ve integrated design management commands directly into the library manager and various editors, making it easier for designers to access the tools they need without leaving their current workflows.
• Streamlined Working Process with Auto Check-In and Check-Out. Our integration platforms automate the check-in and check-out process, simplifying the management of design files from all major electronic design automation (EDA) vendors or in-house tools (via the REST API).
• Advanced Query and Visualisation. We offer a powerful design manager that supports advanced operations, including powerful query capabilities, visualization tools, and hierarchical bill-of-materials (BOM) management.
• Application-Specific Operations. Our platform allows for the management of design operations based on design hierarchy or category, facilitating a more efficient workflow.

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